• Contents • Preface • Acknowledgments • Abbreviations and Symbols • 1. Introduction • 1.1 General Trends • 1.2 The Device Scale Down • 1.3 Frequency Improvements • 1.4 Layers • 1.5 Density • 1.6 Design Trends • 1.7 Market • 1.8 Conclusion • References • Exercises • 2.

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The MOS Devices and Technology • 2.1 Properties of Silicon • 2.2 N-type and P-type Silicon • 2.3 Silicon Dioxide • 2.4 Metal Materials • 2.5 The MOS Switch • 2.6 The MOS Aspect • 2.7 MOS Layout • 2.8 Dynamic MOS Behaviour • 2.9 The Perfect Switch • 2.10 Layout Considerations • 2.11 CMOS Process • 2.12 Conclusion • References • Exercises • 3. The MOS Modelling • 3.1 Introduction to Modelling • 3.2 MOS Model 1 • 3.3 MOS Model 3 • 3.4 The BSIM4 MOS Model • 3.5 Specific MOS Devices • 3.6 Process Variations • 3.7 Concluding Remarks • References • Exercises • 4. The Inverter • 4.1 Logic Symbol • 4.2 CMOS Inverter • 4.3 Inverter Layout • 4.4 Inverter Simulation • 4.5 Power Consumption • 4.6 Static Characteristics • 4.7 Random Simulation • 4.8 The Inverter as a Library Cell • 4.9 3-State Inverter • 4.10 All nMOS Inverters • 4.11 Ring Oscillator • 4.12 Latch-up Effect • 4.13 Conclusion • References • Exercises • 5. Interconnects • 5.1 Introduction • 5.2 Metal Layers • 5.3 Contact and Vias • 5.4 Design Rules • 5.5 Capacitance Associated with Interconnects • 5.6 Resistance Associated with Interconnects • 5.7 Signal Transport • 5.8 Improved Signal Transport • 5.9 Repeaters for Improved Signal Transport • 5.10 Crosstalk Effects in Interconnects • 5.11 Antenna Effect • 5.12 Inductance • 5.13 Conclusion • References • Exercises • 6.